1. Technical Field
The present invention relates to a memory system in which a clock is provided from a memory controller to a memory, and data is output from the memory to the memory controller in synchronization with the clock.
2. Related Art
In connection with a memory system including a memory and a memory controller, acceleration of data transfer between the memory and the memory controller is required. JP-A-2006-40518, JP-A-2001-273765, and JP-A-2006-277892 disclose, as the memory system capable of achieving acceleration of data transfer, a memory that is which are capable of outputting consecutive data in synchronization with a clock externally provided to a semiconductor memory such as, for example, EDO (Extended Data Out) type DRAM, SDRAM (Syncronous DRAM) and the like. In such a memory system data whose address is incremented in synchronization with the clock is output.
Referring to the timing chart of FIG. 9, a description will be given of an exemplary case in which data is output having its address incremented in synchronization with a clock. The clock is a control signal applied from the memory controller to the memory. The data is output from the memory to the memory controller in synchronization with the clock. Prior to data reading, a command that instructs data reading with specifying an address is issued from the memory controller to the memory.
When the clock is output from the memory controller at time t901, the memory starts outputting data (data 1) to a data line by time t903, which is a time point after a certain period with reference to fall of the clock. This period is referred to as the Read Access Time (tREA).
When the clock is output from the memory controller at time t904, the memory stops outputting the previous data at time t905 or later, which is a time point after a certain period with reference to fall of the clock, and the memory starts outputting next data (data 2) whose address is obtained by incrementing the current address, by time t906. The time from t904 to t905 is referred to as the RE Low Output Hold Time (tRLOH). As can be seen from the timing chart, the relationship represented by the following formula is established between the tREA and tRLOH:tREA>tRLOH 
The memory controller can take in the data from the memory at a timing of fall of the clock (for example, t904). While the data take-in can be carried out in a period from t903 to t905, it is assumed herein that the data take-in is carried out in synchronization with the clock of the memory controller.
In this manner, by incrementing the address of data on the memory side in synchronization with fall of the clock, it becomes possible for the memory controller to read data from the memory, without the necessity of outputting the address of read target data to the memory every time.
tREA is a value that is uniquely determined depending on the device capacity of the memory. In order for the memory controller to read data from the memory at the fastest possible speed, the cycle time tRC of the clock must be shortened. However, the memory controller cannot take in the data from the data line when the relationship represented by the following formula is established:tREA>tRC 
Here, when the data output from the memory is taken into the memory controller, the following must be considered. That is, a delay in arrival of the clock from the memory controller to the memory and/or a delay in arrival of the data output from the memory to the memory controller may occur, attributed to capacitive components of the data line between the memory controller and the memory, and the like.
In order to solve the delay problem, there are methods of taking data into the memory controller using a delayed clock, or a clock returned from the memory to the memory controller.
FIG. 10 is a timing chart of a case where clocks are output, e.g., on a five-by-five basis, when the memory controller reads data from the memory. This memory system is provided with, in addition to the clock and the data shown in FIG. 9, a return clock line, through which the clock having been transferred from the memory controller to the memory through the clock line, is returned from the memory to the memory controller.
In this exemplary case, by using the return clock (i.e., the clock having been transferred from the memory controller to the memory through the clock line, and thereafter returned to the memory controller through the return clock line) as the reference, the data output from the memory can be taken in.
However, the memory systems configured as described above still suffer a problem that the piece of data set last cannot be taken in by a single-time command issue. Specifically, while the number of clocks output by a single-time command issue is determined to be a predetermined number, as shown in FIG. 10, because there is no return clock that temporally overlap the fifth piece of data that is output from the memory by the fifth (last) clock, the data take-in with reference to the return clock cannot be carried out. Further, in connection with the sixth to tenth pieces of data, because there is no return clock that temporally overlaps the tenth piece of data that is output by the tenth (last) clock, the data take-in with reference to the return clock cannot be carried out. The same holds true for the pieces of data that follow.
An exemplary solution for this problem is the following method. In order to take in the data of, e.g., fifth piece, take in first to fourth pieces of data, and thereafter issue a command indicative of the address that specifies that the read-start data is the fifth piece of data from the memory controller to the memory, so as to cause the memory to output data again from the fifth piece of data. The same holds true for the tenth piece of data.
However, according to such a method, when commands are consecutively issued for reading data from consecutive addresses, the address of the last piece of data output by the previous command must be specified for each command. Therefore, the associated overhead increases and the data transfer performance of memory system reduces.